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Preliminary Technical Data
FEATURES
Polyphase Energy Metering IC with Phase Drop Indication ADE7762
The only analog circuitry used in the ADE7762 is in the analog-to-digital converters (ADCs) and reference circuit. All other signal processing (for example, multiplication, filtering, and summation) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The ADE7762 supplies average active power information on the low frequency outputs, F1 and F2. These logic outputs can be used to directly drive an electromechanical counter or to interface with an MCU. The CF logic output gives instantaneous active power information. This output is intended to be used for calibration purposes. The ADE7762 includes a power supply monitoring circuit on the VDD pin. The ADE7762 remains inactive until the supply voltage on VDD reaches 4 V. If the supply falls below 4 V, the ADE7762 also resets and no pulses are issued on F1, F2, and CF. A multiple multiplexed logic output provides phase dropout per phase, reverse polarity per phase, and a phase sequence error. Internal phase matching circuitry ensures that the voltage and current channels are phase matched. An internal no load threshold ensures the ADE7762 does not exhibit any creep when there is no load. The ADE7762 is available in a 28-lead SOIC package.
1
High accuracy supports 50 Hz/60 Hz IEC62053-21 Less than 0.1% error over a dynamic range of 500 to 1 Compatible with 3-phase 3-wire delta and 3-phase 4-wire Wye configurations Supplies average active power on the frequency outputs F1 and F2 High frequency output (CF) is intended for calibration and supplies instantaneous active power Logic output REVP indicates a potential miswiring or negative power on the sum of all phases Dropout indication for each phase on LED driver pins Phase sequence error detection Direct drive for electromechanical counters and 2-phase stepper motors (F1 and F2) Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time On-chip power supply monitoring On-chip creep protection (no load threshold) On-chip reference 2.4 V 8% (25 ppm/C typical) with external overdrive capability Single 5 V supply, low power (TBD mW typical) Low cost CMOS process
GENERAL DESCRIPTION
The ADE7762 1 is a high accuracy polyphase electrical energy measurement IC. The ADE7762 specifications surpass the accuracy requirements as quoted in the IEC62053-21 standard.
Patent pending.
ABS
19
FUNCTIONAL BLOCK DIAGRAM
VDD
5
IAP 7 IAN 8 VAP 18
ADC HPF ADC LPF
X
POWER SUPPLY MONITOR
ADE7762
IBP
9
ADC IBN 10 VBP
17
HPF ADC
X LPF
4 21 22
DGND CLKIN CLKOUT
ICP 11 ICN 12 VCP 16 VN 15 2.4V REF 4k ADC ADC HPF LPF X
PHASE AND REVP MONITOR
DIGITAL-TO-FREQUENCY CONVERTER
05757-001
13
14
1
2
28
27
6
20
23
24
25
26
3
AGND
REFIN/OUT LED_CTRL LED_A LED_B LED_C REVP
SCF
S0
S1
F2
F1
CF
Figure 1.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADE7762 TABLE OF CONTENTS
Features .............................................................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions ............................ 7 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 11 Test Circuit ...................................................................................... 12 Theory of Operation ...................................................................... 13 Power Factor Considerations.................................................... 13 Nonsinusoidal Voltage and Current ........................................ 14 Analog Inputs.................................................................................. 15 Current Channels ....................................................................... 15 Voltage Channels ........................................................................ 15 Typical Connection Diagrams ...................................................... 16 Current Channel Connection................................................... 16
Preliminary Technical Data
Voltage Channels Connection .................................................. 16 Meter Connections..................................................................... 16 Power Supply Monitor ................................................................... 18 Phase Monitor................................................................................. 19 HPF and Offset Effects .................................................................. 20 Digital-to-Frequency Conversion ................................................ 21 Mode Selection of the Sum of the Three Active Energies..... 22 Power Measurement Considerations....................................... 22 Transfer Function ........................................................................... 23 Frequency Outputs F1 and F2 .................................................. 23 Frequency Output CF ................................................................ 24 Selecting a Frequency for an Energy Meter Application........... 25 Frequency Outputs..................................................................... 25 No Load Threshold .................................................................... 25 Negative Power Information..................................................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
Rev. PrB | Page 2 of 28
Preliminary Technical Data SPECIFICATIONS
ADE7762
VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = -40C to +85C, unless otherwise noted. Table 1.
Parameter ACCURACY 1, 2 Measurement Error on Current Channel Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Capacitive AC Power Supply Rejection Output Frequency Variation (CF) DC Power Supply Rejection Output Frequency Variation (CF) ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Gain Error REFERENCE INPUT REFIN/OUT Input Voltage Range Input Impedance Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS 3 ACF, S0, S1, and ABS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH Output Low Voltage, VOL CF and NEGP Output High Voltage, VOH Output Low Voltage, VOL LED_CTRL Output Frequency Output High Voltage Output Low Voltage Conditions Voltage channel with full-scale signal (500 mV), 25C, over a dynamic range of 500 to 1 Min Typ 0.1 Max Unit % Reading
0.1 0.1 SCF = 0, S0 = S1 = 1 IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms @ 50 Hz, Ripple on VDD of 200 mV rms @ 100 Hz S1 = 1; S0 = SCF = 0 V1 = 100 mV rms, V2 = 100 mV rms, VDD = 5 V 250 mV See Analog Inputs section VAP - VN, VBP - VN, VCP - VN, IAP - IAN, IBP - IBN, ICP - ICN CLKIN = 10 MHz CLKIN/256, CLKIN = 10 MHz External 2.5 V reference, IA = IB = IC = 500 mV dc 2.4 V + 8% 2.4 V - 8% 2.2 3.3 10 Nominal 2.4 V 200 25 All specifications for CLKIN of 10 MHz 10 370 0.01
Degrees Degrees % Reading
0.1
% Reading
0.5 410 14 25 9 2.6
V peak difference k kHz mV % Ideal V V k pF mV ppm/C MHz
VDD = 5 V 5% VDD = 5 V 5% Typically 10 nA, VIN = 0 V to VDD
2.4 0.8 3 10
V V A pF
ISOURCE = 10 mA, VDD = 5 V ISINK = 10 mA, VDD = 5 V VDD = 5 V, ISOURCE = 5 mA VDD = 5 V, ISINK = 5 mA VDD = 5 V, CLKIN = 10 MHz VDD = 5 V, ISOURCE = 10 mA VDD = 5 V, ISINK = 10 mA
Rev. PrB | Page 3 of 28
4.5 0.5 4.5 0.5 17.39 4.5 TBD
V V V V kHz V V
ADE7762
Parameter LED_A, LED_B, LED_C Output Low ISINK Output High Source POWER SUPPLY VDD IDD
1 2
Preliminary Technical Data
Conditions VDD = 4.75 V VDD = 4.75 V For specified performance 5 V 5% Min TBD TBD 4.75 TBD 5.25 TBD Typ Max Unit mA mA V mA
See the Terminology section for explanation of specifications. See the plots in the Typical Performance Characteristics section. 3 Sample tested during initial release and after any redesign or process changes that might affect this parameter.
Rev. PrB | Page 4 of 28
Preliminary Technical Data
TIMING CHARACTERISTICS
ADE7762
VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = -40C to +85C, unless otherwise noted. Table 2.
Parameter 1,2 t1 3 t2 t3 t43, 4 t5 5 t6 t7 t8 t9
1 2
Conditions F1 and F2 pulse width (logic high) Output pulse period (see the Transfer Function section) Time between F1 falling edge and F2 falling edge CF pulse width (logic high) CF pulse period (see the Transfer Function section) Minimum time between F1 and F2 pulse LED_CTRL pulse width LED_CTRL period LED pulse width
Specification 120
See Figure 2 1/2 t2 90 See Table 7 4/CLKIN 28.8 57.5 7.2
Unit ms sec sec ms sec sec s s s
Sample tested during initial release and after any redesign or process changes that might affect this parameter. See Figure 2. 3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies (see the Frequency Outputs section). 4 CF is not synchronous to F1 or F2 frequency outputs. 5 The CF pulse is always 1 s in the high frequency mode (see the Frequency Outputs section).
t1
F1
t6 t2
F2
t3 t4 t5
05757-002
CF
Figure 2. Timing Diagram for Frequency Outputs
t8 t7
NOT USED
NOT USED
LED1
LED2
LED3
LED4
LED5
LED6
t9
Figure 3: Timing Diagram for LED Drivers
Rev. PrB | Page 5 of 28
05757-003
ADE7762 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP, and ICN Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature 28-Lead SOIC, Power Dissipation JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +7 V -0.3 V to +7 V -6 V to +6 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +150C 150C 63 mW 55C/W 215C 220C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 6 of 28
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LED_CTRL 1 LED_A 2 CF 3 DGND 4 VDD 5 REVP 6 IAP 7
28 27 26 25 24
ADE7762
LED_B LED_C F1 F2 S1
S0 TOP VIEW 22 CLKOUT (Not to Scale) 21 CLKIN IAN 8
23
ADE7762
IBP 9 IBN 10 ICP 11 ICN 12 AGND 13 REFIN/OUT 14
20 19 18 17 16 15
SCF ABS VAP VBP VN
05757-004
VCP
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 Mnemonic LED_CTRL LED_A CF DGND Description LED Control Output. The LED_CTRL signal multiplexes the indication of phase drop, phase sequence error, and per phase reverse power on the LED_A, LED_B, and LED_C pins. Phase A Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power on phase A (see the Phase Monitor section). Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information. This output is intended to be used for calibration purposes. This provides the ground reference for the digital circuitry in the ADE7762, that is, multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7762 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7762. The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled to DGND with a 10 F capacitor in parallel with a 100 nF ceramic capacitor. This logic output goes logic high when negative power is detected on the sum of the three phase powers. This output is not latched and resets when positive power is once again detected (see the Negative Power Information section). Analog Inputs for Current Channels. These channels are intended for use with current transducers and are referenced in this document as current channels. These inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5 V (see the Analog Inputs section). Both inputs have internal ESD protection circuitry; in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This pin provides the ground reference for the analog circuitry in the ADE7762 (ADCs and reference). This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, such as, anti-aliasing filters and current and voltage transducers. To keep ground noise around the ADE7762 to a minimum, the quiet ground plane should only connect to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V 8% and a typical temperature coefficient of 25 ppm/C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F ceramic capacitor. Analog Inputs for the Voltage Channels. These channels are intended for use with voltage transducers and are referenced in this document as voltage channels. These inputs are single-ended voltage inputs with a maximum signal level of 0.5 V with respect to VN for specified operation. All inputs have internal ESD protection circuitry; in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This logic input is used to select the method by which the three active energies from each phase are summed. It selects between the arithmetical sum of the three energies (ABS logic high) or the sum of the absolute values (ABS logic low). See the Mode Selection of the Sum of the Three Active Energies section. Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table 7 shows how the calibration frequencies are selected.
Rev. PrB | Page 7 of 28
5
VDD
6
REVP
7, 8; 9, 10; 11, 12
IAP, IAN; IBP, IBN; ICP, ICN
13
AGND
14
REFIN/OUT
15, 16, 17, 18
VN, VCP, VBP, VAP
19
ABS
20
SCF
ADE7762
Pin No. 21 Mnemonic CLKIN
Preliminary Technical Data
Description Master Clock for the ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7762. The clock frequency for the specified operation is 10 MHz. Ceramic load capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer's data sheet for the load capacitance requirements. A crystal can be connected across this pin and CLKIN as described previously to provide a clock source for the ADE7762. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a crystal is being used. These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion for design flexibility. Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs can be used to drive electromechanical counters and 2-phase stepper motors directly (see the Transfer Function section). Phase C Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power on phase C (see the Phase Monitor section). Phase B Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power on phase B (see the Phase Monitor section).
22
CLKOUT
23, 24 25, 26
S0, S1 F2, F1
27 28
LED_C LED_B
Rev. PrB | Page 8 of 28
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
ADE7762
Figure 5. Error as a Percent of Reading with Internal Reference (Wye Connection)
Figure 8. Error as a Percent of Reading over Temperature with Internal Reference (Wye Connection)
Figure 6. Error as a Percent of Reading over Power Factor with Internal Reference (Wye Connection)
Figure 9. Error as a Percent of Reading over Power Factor with Internal Reference (Delta Connection)
Figure 7. Error as a Percent of Reading over Power Factor with External Reference (Wye Connection)
Figure 10. Error as a Percent of Reading over Temperature with External Reference (Wye Connection)
Rev. PrB | Page 9 of 28
ADE7762
Preliminary Technical Data
Figure 11. Error as a Percent of Reading over Frequency with an Internal Reference (Wye Connection)
Figure 13. Channel 1 Offset Distribution
Figure 12. Error as a Percent of Reading over Power Supply with External Reference (Wye Connection)
Figure 14. Error as a Percent of Reading over Power Supply with Internal Reference (Wye Connection)
Rev. PrB | Page 10 of 28
Preliminary Technical Data TERMINOLOGY
Measurement Error The error associated with the energy measurement made by the ADE7762 is defined by the following formula:
Energy Registered by ADE7762 - True Energy Percentage Error = x 100% True Energy
ADE7762
ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see an analog input signal offset. However, because the HPF is always present, the offset is removed from the current channel and the power calculation is not affected by this offset. Gain Error The gain error of the ADE7762 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7762 transfer function (see the Transfer Function section).
Error between Channels The high-pass filter (HPF) in the current channel has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is placed in the current channel. The phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45 Hz to 65 Hz and 0.2 over a range of 40 Hz to 1 kHz (see Figure 28 and Figure 29). Power Supply Rejection (PSR) This quantifies the ADE7762 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at a nominal supply (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supply and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading. See definition for Measurement Error. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supply is then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading.
Rev. PrB | Page 11 of 28
ADE7762 TEST CIRCUIT
VDD 10F ILOAD 1k RB 33nF 1k
8 IAN
Preliminary Technical Data
100nF
5 19
VDD 7 IAP
ABS F1 26 F2 25 820 CF 3 22pF CLKOUT 22 10MHz CLKIN 21 22pF
K7
1 4
ADE7762
TO FREQ. COUNTER
2 3
33nF SAME AS IAP, IAN
9 IBP 10 IBN 11 ICP 12 ICN 18 VAP
K8
S0 23 S1 24 SCF 20 REFIN/OUT 14 REVP 6
SAME AS IAP, IAN 1M 220V AC 1k 33nF SAME AS VAP SAME AS VAP
1k
VDD
0.1F
10F
17 VBP 16 VCP
LED_CTRL 1 LED_A 2 LED_B 28
15 VN
LED_C 27 AGND DGND
05757-015
1k
33nF
13
4
Figure 15. Test Circuit for Performance Curves
Rev. PrB | Page 12 of 28
Preliminary Technical Data THEORY OF OPERATION
The six signals from the current and voltage transducers are digitized with ADCs. These ADCs are 16-bit second-order - with an oversampling rate of 833 kHz. This analog input structure greatly simplifies transducer interface by providing a wide dynamic range and bipolar input for direct connection to the transducer. High-pass filters in the current channels remove the dc component from the current signals. This eliminates any inaccuracies in the active power calculation due to offsets in the voltage or current signals (see the HPF and Offset Effects section). The active power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals of each phase. In order to extract the active power component, the dc component, the instantaneous power signal is low-pass filtered on each phase. Figure 16 illustrates the instantaneous active power signal and shows how the active power information can be extracted by low-pass filtering the instantaneous power signal. This method is used to extract the active power information on each phase of the polyphase system. The total active power information is then obtained by adding the individual phase active power. This scheme correctly calculates active power for nonsinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time.
p(t) = i(t) x v(t) WHERE: v(t) = V x cos (t) i(t) = I x cos (t) p(t) = V x I {1+ cos (2t)} 2 TIME INSTANTANEOUS POWER SIGNAL - p(t)
ADE7762
The low frequency output of the ADE7762 is generated by accumulating the total active power information. This low frequency inherently means a long accumulation time between output pulses. The output frequency is therefore proportional to the average active power. This average active power information can, in turn, be accumulated (for example, by a counter) to generate active energy information. Because of its high output frequency and therefore shorter integration time, the CF output is proportional to the instantaneous active power. This pulse is useful for system calibration purposes that would take place under steady load conditions.
POWER FACTOR CONSIDERATIONS
Low-pass filtering, the method used to extract the active power information from the individual instantaneous power signal, is still valid when the voltage and current signals of each phase are not in phase. Figure 17 displays the unity power factor condition and a displacement power factor (DPF) = 0.5, that is, current signal lagging the voltage by 60, for one phase of the polyphase. Assuming that the voltage and current waveforms are sinusoidal, the active power component of the instantaneous power signal (the dc term) is given by
V x 1 x cos(60) 2
(1)
VxI VxI 2
VxI 2
INSTANTANEOUS VA x IA + VB x IB + ACTIVE POWER SIGNAL VC x IC 2
HPF IAP IAN ADC MUL TIPLIER VAP ADC HPF IBP IBN ADC MUL TIPLIER VBP ADC HPF ICP ICN ADC MUL TIPLIER VCP VN ADC LPF LPF
ABS INSTANTANEOUS TOTAL POWER SIGNAL
|X|
DIGITAL-TOFREQUENCY LPF |X| DIGITAL-TOFREQUENCY CF F1 F2
|X|
05757-016
Figure 16. Signal Processing Block Diagram
Rev. PrB | Page 13 of 28
ADE7762
This is the correct active power calculation.
INSTANTANEOUS POWER SIGNAL INSTANTANEOUS ACTIVE POWER SIGNAL
Preliminary Technical Data
i(t ) = I O + 2 x
n=0
V I x sin (nt )
n n
(3)
Vx I 2
0V CURRENT VOLTAGE INSTANTANEOUS POWER SIGNAL INSTANTANEOUS ACTIVE POWER SIGNAL
where: i(t) is the instantaneous current. IO is the dc component. In is the rms value of current harmonic n. n is the phase angle of the current harmonic. Using Equations 2 and 3, the active power, P, can be expressed in terms of its fundamental active power (P1) and harmonic active power (PH).
P = P1 + PH
Vx I x cos(60) 2 0V
05757-017
where: P = V 1 x I1 cos 1 1
VOLTAGE 60
1 = 1 - 1
PH =
(4)
CURRENT
Figure 17. DC Component of Instantaneous Power Signal
V
n =1
n
x I n cos n
(5)
NONSINUSOIDAL VOLTAGE AND CURRENT
The active power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications have some harmonic content. Using the Fourier Transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content
n = n - n As can be seen from Equation 5, a harmonic active power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. The power factor calculation has been shown to be accurate in the case of a pure sinusoid. Therefore, the harmonic active power also correctly accounts for power factor since harmonics are made up of a series of pure sinusoids. A limiting factor on harmonic measurement is the bandwidth. On the ADE7762, the bandwidth of the active power measurement is 14 kHz with a master clock frequency of 10 MHz.
v (t ) = Vo + 2 x
n=0
V
n
x sin (nt + n )
(2)
where: v(t) is the instantaneous voltage. VO is the average value. Vn is the rms value of voltage harmonic n. and n is the phase angle of the voltage harmonic.
Rev. PrB | Page 14 of 28
Preliminary Technical Data ANALOG INPUTS
CURRENT CHANNELS
The voltage outputs from the current transducers are connected to the ADE7762 current channels, which are fully differential voltage inputs. IAP, IBP, and ICP are the positive inputs for IAN, IBN, and ICN, respectively. The maximum peak differential signal on the current channel should be less than 500 mV (353 mV rms for a pure sinusoidal signal) for the specified operation.
IAP-IAN +500mV IAP DIFFERENTIAL INPUT 500mV MAX PEAK VCM COMMON-MODE 25mV MAX -500mV VCM
05757-018
ADE7762
VOLTAGE CHANNELS
The output of the line voltage transducer is connected to the ADE7762 at this analog input. Voltage channels are a pseudodifferential voltage input. VAP, VBP, and VCP are the positive inputs with respect to VN. The maximum peak differential signal on the voltage channel is 500 mV (353 mV rms for a pure sinusoidal signal) for specified operation. Figure 19 illustrates the maximum signal levels that can be connected to the ADE7762 voltage channels.
VAP-VN
IA
IAN
+500mV VAP DIFFERENTIAL INPUT 500mV MAX PEAK VCM COMMON-MODE 25mV MAX -500mV VCM
05757-019
AGND
VA
VN
Figure 18. Maximum Signal Levels, Current Channel
AGND
The maximum signal levels on IAP and IAN are shown in Figure 18. The maximum differential voltage between IAP and IAN is 500 mV. The differential voltage signal on the inputs must be referenced to a common mode, for example, AGND. The maximum common-mode signal shown in Figure 18 is 25 mV.
Figure 19. Maximum Signal Levels, Voltage Channel
Voltage channels must be driven from a common-mode voltage, that is, the differential voltage signal on the input must be referenced to a common mode (usually AGND). The analog inputs of the ADE7762 can be driven with common-mode voltages of up to 25 mV with respect to AGND. However, best results are achieved using a common mode equal to AGND.
Rev. PrB | Page 15 of 28
ADE7762 TYPICAL CONNECTION DIAGRAMS
CURRENT CHANNEL CONNECTION
Figure 20 shows a typical connection diagram for the current channel (IA). A current transformer (CT) is the current transducer selected for this example. Notice the common-mode voltage for the current channel is AGND and is derived by center tapping the burden resistor to AGND. This provides the complementary analog input signals for IAP and IAN. The CT turns ratio and burden resistor Rb are selected to give a peak differential voltage of 500 mV at maximum load. In theory it is better to center tap Rb; however, this requires very careful attention to the layout and matching of the resistors to ensure that the channels have the same resistance. A single resistor may be more practical and is a valid design choice.
CT Rb Rf Cf 500mV IAP IAN
Preliminary Technical Data
METER CONNECTIONS
In 3-phase service, two main power distribution services exist: 3-phase 4-wire or 3-phase 3-wire. The additional wire in the 3-phase 4-wire arrangement is the neutral wire. The voltage lines have a phase difference of 120 (2/3 radians) between each other (see Equation 6).
V A (t ) = 2 x V A x cos ( l t ) 2 V B (t ) = 2 x V B x cos l t + 3 4 V C (t ) = 2 x VC x cos l t + 3 where VA, VB, and VC represent the voltage rms values of the different phases. The current inputs are represented by I A (t ) = 2 I A x cos (l t + A ) I B (t ) = 2 I B x cos l t + I C (t ) = 2 I C x cos l t + where: IA, IB, and IC represent the rms value of the current of each phase. A, B, and C represent the phase difference of the current and voltage channel of each phase. The instantaneous powers can then be calculated as follows: PA(t) = VA(t) x IA(t) PB(t) = VB(t) x IB(t) PC(t) = VC(t) x IC(t) Then:
PA (t ) = VA x I A x cos ( A ) - VA x I A x cos (2lt + A )
(6)
PHASE NEUTRAL
Figure 20. Typical Connection for Current Channels
VOLTAGE CHANNELS CONNECTION
Figure 21 shows two typical connections for the voltage channel. The first option uses a potential transformer (PT) to provide complete isolation from the main voltage. In the second option, the ADE7762 is biased around the neutral wire, and a resistor divider is used to provide a voltage signal proportional to the line voltage. Adjusting the ratio of Ra, Rb, and VR is a convenient way of carrying out a gain calibration on the meter. VR can be implemented using either a potentiometer or a binary weighted series of resistors. Either configuration works, however, the potentiometer is subject to noise over time. Two fixed value resistors can be used in place of VR to minimize the noise.
PT 500mV Rf AGND PHASE NEUTRAL Cf Cf Rf Cf VAP VN
05757-020
IP
Rf
Cf
2 + B 3 4 + C 3
(7)
4 + B PB (t ) = VB x I B x cos(B ) - VB x I B x cos 2lt + 3 2 t + 8 + PC (t ) = VC x IC x cos (C ) - VC x IC x cos l C 3
(8)
Ra* Rb* VR*
500mV Rf Cf
VAP VN
05757-021
As shown in Equation 8, in the ADE7762, the active power calculation per phase is made when current and voltage inputs of one phase are connected to the same channel (A, B, or C). Then the summation of each individual active power calculation gives the total active power information, P(t) = PA(t) + PB(t) + PC(t).
PHASE NEUTRAL
* Ra >> Rf + VR; * Rb + VR = Rf
Figure 21. Typical Connections for Voltage Channels
Rev. PrB | Page 16 of 28
Preliminary Technical Data
Figure 22 shows the connections of the ADE7762 analog inputs with the power lines in a 3-phase 3-wire delta service.
Ra* Rb* VR* Rb* CT PHASE A
PHASE A
ADE7762
Figure 23 shows the connections of the ADE7762 analog inputs with the power lines in a 3-phase 4-wire Wye service.
Ra* Rb* Cf
Cf
VAP IAP IAN ANTIALIASING FILTERS
VR* Rb* CT ANTIALIASING FILTERS CT
VAP IAP IAN
PHASE C SOURCE Rf CT PHASE B ANTIALIASING FILTERS IBP IBN VBP
05757-022
SOURCE
PHASE B
Ra* Rb*
Cf Rb*
ANTIALIASING FILTERS IBP IBN VBP
VN Cf
LOAD
PHASE C
VR* CT
Ra* Rb* VR*
Cf
Rb*
Ra* Rb* VR* Rf
Cf Rb*
ANTIALIASING FILTERS ICP ICN VCP LOAD
* Ra >> Rf + VR; * Rb + VR = Rf
Figure 22. 3-Phase 3-Wire Meter Connection with ADE7762
CF
* Ra >> Rf + VR; * Rb + VR = Rf
Figure 23. 3-Phase 4-Wire Meter Connection with ADE7762
Note that only two current inputs and two voltage inputs of the ADE7762 are used in this case. The active power calculated by the ADE7762 does not depend on the selected channels.
Rev. PrB | Page 17 of 28
05757-023
VN
ADE7762 POWER SUPPLY MONITOR
The ADE7762 contains an on-chip power supply monitor. The power supply (VDD) is monitored continuously by the ADE7762. At power up, when the supply is less than 4V 2% and VREF is less than 1.9 V (typ), the outputs of the ADE7762 are inactive and the data path is held in reset. Once VDD is greater than 4V 2% and VREF is greater than 1.9 V (typ), the chip is active and energy accumulation begins. At power-down, when VDD falls below 4 V or VREF falls below 1.9 V (typ), the data path is again held in reset. This implementation ensures correct device operation at powerup and at power-down. The power supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. The power supply and decoupling for the part should be such that the ripple at VDD does not exceed 5% as specified for normal operation.
5V 4V
Preliminary Technical Data
VDD
2.4V 1.9V
VREF
0V
INTERNAL INACTIVE RESET
ACTIVE
INACTIVE
Figure 24. On-Chip Power Supply Monitor
Rev. PrB | Page 18 of 28
05757-024
Preliminary Technical Data PHASE MONITOR
The ADE7762 has phase monitoring functions to detect phase dropout, phase sequence error, and reverse polarity using four pins. Phase dropout has the highest priority, and reverse polarity has lowest priority. If a phase dropout occurs, phase sequence error indication is disabled until all three phases are above the phase dropout level (see the Phase Dropout Error section). Because the dropout detection level is not set to zero, a phase can have some small voltage during phase dropout condition. Therefore, reverse polarity is still indicated on that phase if the proper conditions occur. The phase monitor circuit functions by multiplexing signals onto the four pins. The four multiplexed pins are LED_CTRL, LED_A, LED_B, and LED_C. Two LEDs can be connected to each pin as shown in Figure 25. When LED_CTRL is high, LED_A would be low to turn on an LED and indicate a phase drop condition on Phase A. When LED_CTRL is low, LED_A is high to indicate a reverse polarity (REVP) condition on phase A. Phase sequence error is indicated by blinking the Phase Seq/Drop LEDs. LED_CTRL switches at a rate of 131 kHz so that both the Phase Seq/Drop LEDs and REVP LEDs can appear to be on simultaneously, which allows indication of phase dropout and REVP at the same time. For the timing diagram, see Figure 3.
PHASE SEQ/DROP PHASE SEQ/DROP REVP PHASE SEQ/DROP REVP RLOAD LED_C RLOAD LED_B
05757-025
ADE7762
Phase Sequence Error
The ADE7762 detects the zero crossing of each phase. A phase sequence error occurs when the sequence A>B>C>A> ... is violated. If a phase sequence error occurs, the Phase Seq/Drop LEDs blink at 1 Hz (see Figure 26). Phase sequence error and REVP can be displayed simultaneously. The REVP LEDs continue to indicate reverse polarity if the proper conditions exist. For example, if the phase sequence becomes A>C>B>A... and phase B has negative active energy accumulated, then the REVP LED for phase B is on solid and all of the Phase Seq/Drop LEDs would be blinking at 1 Hz. The delay in indicating the phase sequence error with blinking LEDs is approximately 150 ms from the time that a phase sequence error occurs.
80% FS A = 0 B = -120 C = +120
VOLTAGE WAVEFORMS
RISING EDGE ZERO CROSSINGS A
B
C
A
B
C
PHASE SEQ/DROP LEDS ARE OFF.
LED_CTRL
80% FS
A = 0
C = -120
B = +120
REVP RLOAD LED_A
VOLTAGE WAVEFORMS
RISING EDGE ZERO CROSSINGS A
C
B
A
C
B
PHASE SEQ/DROP LEDS ARE BLINKING AT 1Hz.
Figure 25. Phase Monitor Circuit
80% FS
A = 0
C = -120
Phase Dropout Error
The ADE7762 indicates a phase drop condition when there is low voltage signal or no voltage signal on a phase. The phase dropout condition occurs when the amplitude of the phase drops below 20% of full-scale analog input voltage or when a zero crossing is not followed by another zero crossing on that phase for 150 ms. When this occurs, a phase dropout signal is generated and the Phase Seq/Drop LED is turned on for the missing phase. The delay between the phase drop condition occurring at the analog inputs and indication of the condition on the LED outputs is approximately 150 ms. During a phase dropout condition, energy continues to accumulate on the dropped channel, as well as the other channels, and phase sequence error indication is disabled. The Phase Seq/Drop LED for the dropped phase is turned off when the zero crossings return for more than 150 ms and there is more than 20% of fullscale input voltage on the voltage input of that phase.
20% FS VOLTAGE WAVEFORMS
B = +120
RISING EDGE ZERO CROSSINGS A
B
C
A
B
C
PHASE SEQ/DROP LED FOR PHASE B IS ON.
Figure 26. Phase Sequence Detection
Reverse Polarity Error
When reverse power is detected on any phase, the corresponding REVP LED turns on for that phase. For example, if the power for phase A is negative, the REVP LED connected to LED_A turns on. The indication of REVP on the LED_A, LED_B, or LED_C pins is nearly instantaneous. As soon as the input to the ADCs changes and the power is calculated such that there is a reverse power condition on any phase, the appropriate LED is turned on.
Rev. PrB | Page 19 of 28
05757-030
ADE7762 HPF AND OFFSET EFFECTS
Figure 27 shows the effect of offsets on the active power calculation. An offset on the current channel and voltage channel contributes a dc component after multiplication as shown in Figure 27. Since this dc component is extracted by the LPF and is used to generate the active power information for each phase, the offsets can contribute a constant error to the total active power calculation. The HPF in the current channels avoids this problem easily. By removing the offset from at least one channel, no error component can be generated at dc by the multiplication. Error terms at cos(t) are removed by the LPF and the digital-to-frequency conversion (see the Digital-toFrequency Conversion) section.
Preliminary Technical Data
The ADE7762 is phase compensated up to 1 kHz as shown. This ensures correct active harmonic power calculation even at low power factors.
{V cos(t ) + VOS }x {I cos(t ) + I OS } =
+ VOS x I OS + VOS x I cos(t ) + I OS x V cos(t ) (9) 2 VxI + x cos(2t ) 2
VxI
Figure 28. Phase Error between Channels (0 Hz to 1 kHz)
VOS x IOS Vx I 2
DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULA TION
IOS x V
05757-026
VOS x I 0 2 FREQUENCY - RAD/S
Figure 27. Effect of Channel Offset on the Active Power Calculation
The HPF in the current channels has an associated phase response that is compensated for on-chip. Figure 28 and Figure 29 show the phase error between channels with the compensation network.
Figure 29. Phase Error Between Channels (40 Hz to 70 Hz)
Rev. PrB | Page 20 of 28
Preliminary Technical Data DIGITAL-TO-FREQUENCY CONVERSION
After multiplication, the digital output of the low-pass filter contains the active power information of each phase. However, since this LPF is not an ideal brick wall filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, that is, cos(ht), where h = 1, 2, 3 .... The magnitude response of the filter is given by
|H ( f )| = 1 f 1+ 8
2
ADE7762
The average value of a sinusoidal signal is zero. Thus, the frequency generated by the ADE7762 is proportional to the average active power. Figure 30 shows the digital-to-frequency conversion for steady load conditions, that is, constant voltage and current. The frequency output CF varies over time, even under steady load conditions (see Figure 30). This frequency variation is primarily due to the cos(2t) components in the instantaneous active power signal. The output frequency on CF can be up to 160x higher than the frequency on F1 and F2. The higher output frequency is generated by accumulating the instantaneous active power signal over a much shorter time, while converting it to a frequency. This shorter accumulation period means less averaging of the cos(2t) component. Therefore, some of this instantaneous power signal passes through the digital-to-frequency conversion. Where CF is used for calibration purposes, the frequency counter should average the frequency to remove the ripple and obtain a stable frequency. If CF is being used to measure energy, for example, in a microprocessor-based application, the CF output should also be averaged to calculate power. Because the outputs F1 and F2 operate at a much lower frequency, significant averaging of the instantaneous active power signal is carried out. The result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output on F1 and F2, which are used to measure energy in a stepper-motor based meter.
(10)
where the -3 dB cutoff frequency of the low-pass filter is 8 Hz. For a line frequency of 50 Hz, this would give an attenuation of the 2(100 Hz) component of approximately -22 dB. The dominating harmonic is twice the line frequency, that is, cos(2t), due to the instantaneous power signal. Figure 30 shows the instantaneous active power signal at the output of the CF, which still contains a significant amount of instantaneous power information, cos(2t). This signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time to produce an output frequency. This accumulation of the signal suppresses or averages out any non-dc component in the instantaneous active power signal.
VA LPF MULTIPLIER IA
ABS
|X|
F1 DIGITAL-TOFREQUENCY
VB LPF MULTIPLIER IB |X|
F1 F2 DIGITAL-TOFREQUENCY
FREQUENCY
TIME CF CF
VC LPF MULTIPLIER IC LPF TO EXTRACT REAL POWER (DC TERM) |X| Vx I 2
FREQUENCY
TIME
cos(2t) ATTENUATED BY LPF
0
INSTANTANEOUS REAL POWER SIGNAL (FREQUENCY DOMAIN)
Figure 30. Active Power-to-Frequency Conversion
Rev. PrB | Page 21 of 28
05757-029
2 FREQUENCY - RAD/S
ADE7762
POWER MEASUREMENT CONSIDERATIONS
Calculating and displaying power information always have some associated ripple that depends on the integration period used in the MCU to determine average power as well as the load. For example, at light loads, the output frequency can be 10 Hz. With an integration period of two seconds, only about 20 pulses are counted. The possibility of missing one pulse always exists since the ADE7762 output frequency is running asynchronously to the MCU timer. This would result in a 1-in-20 or 5% error in the power measurement. To remedy this, an appropriate integration time should be considered to achieve the desired accuracy.
Preliminary Technical Data
MODE SELECTION OF THE SUM OF THE THREE ACTIVE ENERGIES
The ADE7762 can be configured to execute the arithmetic sum of the three active energies, Wh = WhA + WhB + WhC, or the sum of the absolute value of these energies, Wh = |WhA| + |WhB| + |WhC|. The selection between the two modes can be made by setting the ABS pin. Logic high and logic low applied on the ABS pin correspond to the arithmetic sum and the sum of absolute values, respectively. When the sum of the absolute values is selected, the active energy from each phase is always counted positive in the total active energy. It is particularly useful in 3-phase 4-wire instillation where the sign of the active power should always be the same. If the meter is misconnected to the power lines, that is, CT connected in the wrong direction then the total active energy recorded without this solution can be reduced by twothirds. The sum of the absolute values assures that the active energy recorded represents the actual active energy delivered. In this mode, the reverse power pin still detects when negative power is present on any of the three phase inputs, but energy continues to accumulate regardless of the sign.
Rev. PrB | Page 22 of 28
Preliminary Technical Data TRANSFER FUNCTION
FREQUENCY OUTPUTS F1 AND F2
The ADE7762 calculates the product of six voltage signals (on current channel and voltage channel) and then low-pass filters this product to extract active power information. This active power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active high pulses. The pulse rate at these outputs is relatively low, for example, 2.01 Hz maximum for ac signals with SCF = S0 = 0; S1 = 1 (see Table 6). This means that the frequency at these outputs is generated from active power information accumulated over a relatively long period. The result is an output frequency that is proportional to the average active power. The averaging of the active power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation:
Freq = 6.181 x (VAN x I A + VBN x I B + VCN x IC ) x F 1-7 VREF 2
ADE7762
Example 1
Thus, if full-scale differential dc voltages of +500 mV are applied to VA, VB, VC, IA, IB, and IC, respectively (500 mV is the maximum differential voltage that can be connected to current and voltage channels), then the expected output frequency is calculated as follows: F1-7 = 0.58 Hz, SCF = S0 = S1 = 1 VAN = VBN = VCN = IA = IB = IC = 500 mV dc = 0.5 V(rms of dc = dc) VREF = 2.4 V (nominal reference value) Note that if the on-chip reference is used, actual output frequencies can vary from device to device due to reference tolerance of 8%.
Freq = 3 x 6.181 x 0.5 x 0.5 x 0.58 2.4 2 = 0.467 Hz
(12)
(11)
Example 2
In this example, with ac voltages of 500 mV peak applied to the voltage channels and current channels, the expected output frequency is calculated as follows:
F1- 7 = 0.58 Hz, SCF = S0 = S1 = 1 VAN = VBN = VCN = IA = IB = IC 2 VREF = 2.4 V (nominal reference value) = 500 mV peak AC = 0.5 Vrms
where: Freq = output frequency on F1 and F2 (Hz). VAN, VBN, and VCN = differential rms voltage signal on voltage channels (V). IA, IB, and IC = differential rms voltage signal on current channels (V). VREF = the reference voltage (2.4 V 8%) (V). F1-7 = one of seven possible frequencies selected by using the logic inputs SCF, S0, and S1 (see Table 5).
Table 5. F1-7 Frequency Selection1
SCF 0 1 0 1 0 1 0 1
1
(13)
Note that if the on-chip reference is used, actual output frequencies can vary from device to device due to reference tolerance of 8%.
Freq = 3 x 6.181 x 0.5 x 0.5 x 0.58 2 x 2 x 2.42 = 0.233 Hz
S1 0 0 0 0 1 1 1 1
S0 0 0 1 1 0 0 1 1
F1-7 (Hz) 2.30 4.61 1.15 4.61 5.22 1.15 0.58 0.58
(14)
F1-7 is a fraction of the master clock and therefore varies if the specified CLKIN frequency is altered.
As can be seen from these two example calculations, the maximum output frequency for ac inputs is always half of that for dc input signals. The maximum frequency also depends on the number of phases connected to the ADE7762. In a 3-phase 3-wire delta service, the maximum output frequency is different from the maximum output frequency in a 3-phase 4-wire Wye service. The reason is that there are only two phases connected to the analog inputs, but also that in a delta service, the current channel input and voltage channel input of the same phase are not in phase in normal operation.
Rev. PrB | Page 23 of 28
ADE7762
Example 3
In this example, the ADE7762 is connected to a 3-phase 3-wire delta service as shown in Figure 22. The total active energy calculation processed in the ADE7762 can be expressed as Total Active Power = (VA - VC) x IA + (VB - VC) x IB where: VA, VB, and VC represent the voltage on phase A, phase B, and phase C, respectively. IA and IB represent the current on phase A and phase B, respectively. As the voltage and current inputs respect Equations 5 and 6, the total active power (P) is
P = (VA - VC )
Preliminary Technical Data
Note that if the on-chip reference is used, actual output frequencies can vary from device to device due to reference tolerance of 8%.
Freq = 2 x 6.181 x 0.5 x 0.5 x 0.60 2 x 2 x 2.4 2 x 3 = 0.139 Hz 2
(20)
Table 6 shows a complete listing of all maximum output frequencies when using all three channel inputs.
Table 6: Maximum Output Frequency on F1 and F2
Maximum Frequency for AC Inputs (Hz) 0.93 1.86 0.46 1.86 2.10 0.46 0.23 0.23 Maximum Frequency for DC Inputs (Hz) 1.85 3.71 0.93 3.71 4.20 0.93 0.47 0.47
SCF 0 1 0 1 0 1 0 1
S1 0 0 0 0 1 1 1 1
S0 0 1 1 1 0 0 1 1
(IAP - IAN ) + (VB - VC ) x (IBP - IBN )
(15)
4 P = 2 x V A x cos( l t ) - 2 x VC x cos l t + 3 x 2 x I A x cos( l t ) 4 2 + 2 x V B x cos l t + - v 2 x VC x cos l t + 3 3 2 x 2 x I B x cos l t + 3
FREQUENCY OUTPUT CF
The pulse output calibration frequency (CF) is intended for use during calibration. The output pulse rate on CF can be up to 64x the pulse rate on F1 and F2. Table 7 shows how the two frequencies are related, depending on the states of the logic inputs S0, S1, and SCF. Because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous active power. As is the case with F1 and F2, the frequency is derived from the output of the low-pass filter after multiplication. However, since the output frequency is high, this active power information is accumulated over a much shorter time. Thus, less averaging is carried out in the digital-tofrequency conversion. The CF output is much more responsive to power fluctuations with much less averaging of the active power signal (see Figure 16).
Table 7. Maximum Output Frequency on CF
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1-7 (Hz) 2.3 4.61 1.15 4.61 5.22 1.15 0.58 0.58 CF Maximum for AC Signals (Hz) 16 x F1, F2 = 14.88 8 x F1, F2 = 14.88 32 x F1, F2 = 14.88 16 x F1, F2 = 29.76 160 x F1, F2 = 336 16 x F1, F2 = 7.36 32 x F1, F2 = 7.36 16 x F1, F2 = 3.68
For simplification, assume that A = B = C = 0 and VA = VB = VC = V. The preceding equation becomes
2 2 P = 2 x V x I A x sin x sin l t + x cos(l t ) 3 3 2 + 2 x V x I B x sin x sin(l t + )x cos l t + 3 3
(16)
P then becomes
2 2 P = VAN x I A x sin + sin 2 l t + 3 3 + VBN x I B x sin + sin 2 l t + 3 3
(17)
where: VAN = V x sin(2/3). VBN = V x sin(/3). As the LPF on each channel eliminates the 2l component of the equation, the active power measured by the ADE7762 is P = V AN x I A x 3 3 + V BN x I B x 2 2 (18)
If full-scale ac voltage of 500 mV peak is applied to the voltage channels and current channels, the expected output frequency is calculated as follows:
F1- 7 = 0.60Hz, SCF = S0 = S1 = 1 VAN = VBN = IA = IB = IC = 500 mV peak ac = VCN = IC = 0 VREF = 2.4V nominal reference value 0.5 2 V rms
(19)
Rev. PrB | Page 24 of 28
Preliminary Technical Data SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION
As shown in Table 5, the user can select one of seven frequencies. This frequency selection determines the maximum frequency on F1 and F2. These outputs are intended to be used to drive the energy register (electromechanical or other). Since seven different output frequencies can be selected, the available frequency selection has been optimized for a 3-phase 4-wire service with a meter constant of 100 imp/kWhr and a maximum current of between 10 A and 100 A. Table 8 shows the output frequency for several maximum currents (IMAX) with a line voltage of 220 V (phase neutral). In all cases, the meter constant is 100 imp/kWhr.
Table 8. F1 and F2 Frequency at 100 imp/kWhr
IMAX (A) 10 25 40 60 80 100 F1 and F2 (Hz) 0.18 0.46 0.73 1.10 1.47 1.83
ADE7762
When selecting a suitable F1-7 frequency for a meter design, the frequency output at IMAX (maximum load) with a 100 imp/kWhr meter constant should be compared with Column 5 of Table 9. The frequency that is closest in Table 9 determines the best choice of frequency (F1-7). For example, if a 3-phase 4-wire Wye meter with a 25 A maximum current is being designed, the output frequency on F1 and F2 with a 100 imp/kWhr meter constant is 0.46 Hz at 25 A and 220 V (see Table 8). Looking at Table 9, the closest frequency to 0.46 Hz in Column 5 is 0.53 Hz. Therefore, F1-7 = 5.22 Hz is selected for this design.
FREQUENCY OUTPUTS
Figure 2 shows a timing diagram for the various frequency outputs. The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two alternating high going pulses. The pulse width (t1) is set at 120 ms, and the time between the rising edges of F1 and F2 (t3) is approximately half the period of F1 (t2). If, however, the period of F1 and F2 falls below 550 ms (1.81 Hz), the pulse width of F1 and F2 is set to half of their period. The maximum output frequencies for F1 and F2 are shown in Table 6. The high frequency CF output is intended to be used for communications and calibration purposes. CF produces a 90 mswide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table 7. As in the case of F1 and F2, if the period of CF (t5) falls below 190 ms, the CF pulse width is set to half the period. For example, if the CF frequency is 20 Hz, the CF pulse width is 25 ms.
The F1-7 frequencies allow complete coverage of this range of output frequencies on F1 and F2. When designing an energy meter, the nominal design voltage on the voltage channels should be set to half scale to allow for calibration of the meter constant. The current channel should also be no more than half scale when the meter sees maximum load. This allows overcurrent signals and signals with high crest factors to be accommodated. Table 9 shows the output frequency on F1 and F2 when all six analog inputs are half scale.
Table 9. F1 and F2 Frequency with Half-Scale AC Inputs
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1-7 (Hz) 2.3 4.61 1.15 4.61 5.22 1.15 0.58 0.58 Frequency on F1 and F2 (Half-Scale AC Inputs) (Hz) 0.23 0.46 0.12 0.46 0.53 0.12 0.06 0.06
NO LOAD THRESHOLD
The ADE7762 includes no load threshold and start-up current circuitry features that eliminate any creep effects in the meter. The circuit is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum output frequency does not cause a pulse to be issued on F1, F2, or CF. The no-load threshold is determined by the sum of all phases. The minimum output frequency is given as 0.0075% of the fullscale output frequency for each of the F1-7 frequency selections, or approximately 0.0029% of the F1-7 frequency (see Table 10). For example, for an energy meter with a 100 imp/kWhr meter constant using F1-7 (4.61 Hz), the minimum output frequency at F1 or F2 would be 13.35 x 10-5 Hz. This would be 2.13 x 10-3 Hz at CF (16 x F1 Hz). In this example, the no load threshold would be equivalent to 4.8 W of load or a start-up current of 20.03 mA at 240 V.
Rev. PrB | Page 25 of 28
ADE7762
Table 10. CF, F1, and F2 Minimum Frequency at No Load Threshold
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1, F2 Minimum (Hz) 6.94E - 05 1.39E - 04 3.47E - 05 1.39E - 04 1.58E - 04 3.47E - 05 1.75E - 05 1.75E - 05 CF Minimum (Hz) 1.11E - 03 1.11E - 03 1.11E - 03 2.23E - 03 2.52E - 02 5.55E - 04 5.60E - 04 2.80E - 04
Preliminary Technical Data
NEGATIVE POWER INFORMATION
The ADE7762 detects when total power, calculated as the sum of the three phases, is negative. This mechanism can detect an incorrect connection of the meter or generation of negative active energy. The REVP pin output goes active high when negative power is detected on the sum of the three phase inputs. If positive active power is detected on the sum of three phases, then REVP pin output is low. The REVP pin output changes state at the same time as a pulse is issued on CF. If the sum of the phases measure negative power, then the REVP pin output stays high until the sum of the phases measures positive power.
Rev. PrB | Page 26 of 28
Preliminary Technical Data OUTLINE DIMENSIONS
18.10 (0.7126) 17.70 (0.6969)
28 15
ADE7762
7.60 (0.2992) 7.40 (0.2913)
1 14
10.65 (0.4193) 10.00 (0.3937)
2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10
0.75 (0.0295) x 45 0.25 (0.0098)
8 1.27 (0.0500) 0.51 (0.0201) SEATING 0.33 (0.0130) 0 BSC 0.31 (0.0122) PLANE 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADE7762ARWZ 1 ADE7762ARWZ-RL1 ADE7762ARW ADE7762ARW-RL EVAL-ADE7762EB
1 2
Package Description 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] ADE7762 Evaluation Board
Package Option RW-28 2 RW-28 on 13" Reels RW-28 RW-28 on 13" Reels
Z = Pb-free part. RW = small outline wide body package in tubes.
Rev. PrB | Page 27 of 28
ADE7762 NOTES
Preliminary Technical Data
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05757-0-1/06(PrB)
Rev. PrB | Page 28 of 28

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